Vervesemi India fabless semiconductor startup $10 million Series A funding 2026

Vervesemi Raises $10M Series A: India’s Fabless Semiconductor Startup Is Building Chips for Space, Defence & AI

Soumya Verma
16 Min Read

QUICK TAKE :

Company: Vervesemi Microelectronics Pvt Ltd — Fabless semiconductor startup, Noida. Founded 2017
Founders: Rakesh Malik (Co-founder & CEO) + Pratap Narayan Singh (Co-founder & CTO) — veterans from global semiconductor multinationals
Round: $10 Million — Series A, multiple times oversubscribed. Prior raise: $500,000 (seed)
Lead Investors: Ashish Kacholia (Lucky Investment Managers) + Unicorn India Ventures — co-led
Co-investors: Roots Ventures · Caperize Fina · MAIQ Growth Scheme · Multiple HNIs
Tech: ML-enhanced analog + mixed-signal ICs; 140+ semiconductor IP blocks; 25 IC product variants; 10 patents + 5 trade secrets
Markets: Space · Defence · Industrial · Motor Control · Smart Energy · Avionics — mission-critical applications
Gov Cred: First DLI Scheme recognized company; MeitY C2S project (BLDC controller IC); Samsung SAFE + UMC IP Alliance Partner

WHAT DOES VERVESEMI ACTUALLY DO? (PLAIN ENGLISH)

 Fabless = Design Without A Factory
  • A ‘fabless’ semiconductor company designs chips but does not own the physical factory (fab) to make them. It outsources fabrication to foundries like Samsung or TSMC. Think of it like a fashion designer who creates the patterns but sends them to a factory to be sewn.
  • Vervesemi’s specialty: ‘Analog and mixed-signal ICs’. Analog chips are the bridge between the real world (temperature, pressure, sound, voltage) and the digital world. They are in every power supply, every sensor, every motor controller. They are not glamorous like Nvidia’s GPUs — but they are irreplaceable.
  • The ML layer: Vervesemi adds machine learning directly into the analog architecture. This means their chips can self-calibrate, improve yield, and adapt to operating conditions without external software — critical for space and defence applications where there is no internet connection and no room for error.
  • Customers include: a leading Indian space organisation (ISRO-adjacent), multiple global OEMs, and industrial players in motor control and smart energy. These are not pilots or proof-of-concepts — they are production contracts.

THE STORY

 Noida-based fabless semiconductor startup Vervesemi Microelectronics announced a $10 million Series A round — co-led by ace market investor Ashish Kacholia (Lucky Investment Managers) and deep tech-focused VC Unicorn India Ventures, with participation from Roots Ventures, Caperize Fina, and MAIQ Growth Scheme. The round, which was multiple times oversubscribed, takes Vervesemi’s total funding from $500,000 to over $10.5 million and marks the company’s shift from technology validation to scaled commercial deployment. Founded in 2017 by Rakesh Malik (CEO) and Pratap Narayan Singh (CTO) — both veterans from global semiconductor multinationals — Vervesemi has spent nine years building what may be India’s most credentialed fabless chip IP portfolio: 140+ semiconductor IP blocks, 25 IC product variants, 10 patents, and confirmed production orders from a leading Indian space organisation and multiple global customers.

WHY THIS MATTERS

India’s semiconductor story has so far been dominated by the fab narrative — who will build the first chip factory, how much will the government subsidise it, when will the first wafer roll out. Vervesemi is a reminder that the design layer — where the real intellectual property and margin live — is already happening, quietly, in Noida. An oversubscribed $10M raise with Ashish Kacholia on the cap table is the kind of signal that matters: Kacholia does not chase hype. His bets are built on sustained technology moats and verified revenue. The fact that this round closed multiple times oversubscribed suggests strong HNI and institutional appetite for Indian semiconductor IP — a category that was nearly unfundable five years ago.

Three Strategic Uses of the $10 Million

# Strategic Priority Detail & Why It Matters
1 Product Commercialisation Accelerate ML-enhanced analog signal chain IC portfolio: advanced data converters, intelligent power + sensing solutions for industrial, smart energy, motor control, and avionics. Move from ‘design validation’ to production-grade volumes for global OEMs.
2 Production Ramp + IP Expansion Take existing silicon chips from lab to production qualification. Scale engineering and applications teams to support global customer orders. Expand IP portfolio and strengthen R&D in next-generation precision analog architectures. Multiple tape-outs in pipeline across advanced nodes.
3 Global GTM: Asia, US & Beyond Build go-to-market presence across Asia, US, and other key semiconductor markets. Deepen engagement with OEMs and system integrators. This is not a ‘India-first’ business — Vervesemi is positioning as a global analog IP supplier from day one.

The Investors: What Ashish Kacholia Backing Means

Investor Type Why Their Bet Matters
Ashish Kacholia (Lucky Investment Managers) HNI / Ace Investor Kacholia is India’s most-watched small/mid-cap stock investor. His entry into deep tech startups — particularly a 7-year-old analog chip company with no consumer brand — signals genuine technical conviction, not trend-chasing. Known for spotting compounders early.
Unicorn India Ventures (Anil Joshi) Seed/Early-Stage VC India’s most dedicated deep tech seed fund. Has backed 50+ deep tech startups. Anil Joshi’s comment: ‘fabless semicon design companies are leading the pack’ — a validation of the entire category, not just Vervesemi.
Roots Ventures VC / Angel Emerging deep tech-focused investor; part of a growing cohort of funds building semiconductor startup portfolios in India alongside the ISM 2.0 policy wave
Caperize Fina + MAIQ Growth Scheme PE / Growth Institutional participation from growth-stage capital vehicles; MAIQ Growth Scheme is particularly notable as it indicates institutional asset manager interest in the deep tech category
Multiple HNIs Angel / HNI Pool The oversubscribed nature suggests strong HNI appetite — typical of deals where a marquee name (Kacholia) has already committed and signals conviction to the wider investor network

Vervesemi’s 5 Verified Technical Moats

  • 140+ Semiconductor IP Blocks + 25 IC Product Variants: This is not a one-chip startup. Vervesemi has built a portfolio that spans multiple application domains, giving it cross-selling leverage across industrial, space, and energy verticals.
  • 10 Patents + 5 Trade Secrets: In semiconductor design, IP protection is everything. A trade secret in analog design is often more valuable than a patent — it means the architecture cannot be reverse-engineered even after the chip is in production.
  • Samsung SAFE + UMC IP Alliance Partner: Vervesemi’s chips are validated on Samsung’s FinFET nodes (advanced CMOS) and UMC’s process nodes. Being an IP alliance partner means foundry engineers actively co-optimize Vervesemi’s designs — a privilege reserved for verified, high-quality IP.
  • First DLI Scheme Recognized Company: The Design Linked Incentive (DLI) Scheme under MeitY provides financial + technical support to fabless chip startups. Being the first recognized company means Vervesemi’s IP quality passed India’s highest government-level chip design scrutiny.
  • Space-Grade Silicon Customer Win: A confirmed chip development project for a ‘leading space organisation’ (widely understood to be ISRO-adjacent) is not a POC — it is a production contract with the most stringent reliability requirements in electronics. This validates the ML-enhanced architecture at the toughest possible application tier.

 

“This Series A funding marks a defining milestone for Vervesemi. The round was multiple times oversubscribed, and the backing of Ashish Kacholia, Unicorn India Ventures, and other distinguished investors reinforces our conviction that world-class semiconductor innovation can originate from India. This funding allows us to move from technology validation to large-scale deployment, positioning Vervesemi as a global supplier of intelligent analog mixed signal semiconductor solutions.”  — Rakesh Malik, Co-founder & CEO, Vervesemi Microelectronics

“This funding enables us to transition from advanced R&D to scaled market execution. We are accelerating product tape-outs, expanding our engineering capabilities, and strengthening our global go-to-market presence. Our mission is to redefine how precision mixed signal SOCs are designed and deployed worldwide.”  — Pratap Narayan Singh, Co-founder & CTO, Vervesemi Microelectronics

“Vervesemi has a set of founders with rich experience from leading multinationals and deep domain expertise in Analog and Digital processing. This has been validated by order wins from marquee customers including a leading space organisation for their chip and multiple global customers for their semiconductor IPs. The Indian Deep Tech innovation ecosystem is taking shape fast.”  — Ashish Kacholia, Founder, Lucky Investment Managers

India’s Semiconductor Policy Tailwind: ISM 2.0 + Budget 2026

Vervesemi’s raise does not happen in a policy vacuum. Budget 2026 (February 1, 2026) delivered the most comprehensive semiconductor policy package India has ever announced:

Policy / Scheme Outlay What It Means for Fabless Startups
India Semiconductor Mission 2.0 (ISM 2.0) ₹1,000 crore (FY27 initial) Full-stack Indian IP focus; equipment + materials + design; industry-led R&D centres; transition from ecosystem creation to global integration
Electronics Component Manufacturing Scheme (ECMS) ₹40,000 crore (from ₹22,919 crore) Nearly doubled on the back of investment commitments already 2x the original target; ECMS funds component supply chain that fabless cos depend on
Design Linked Incentive (DLI) Scheme Operational — MeitY 24 startups funded; ₹430 crore VC attracted to DLI portfolio; 16 tape-outs + 6 chips fabricated at advanced nodes (including 12nm). Vervesemi was first recognized company.
C2S (Chips to Startup) Programme MeitY — ongoing BLDC controller IC project awarded to Vervesemi; bridges academia–industry chip design gap; 67,000 students + 1,000 startup engineers using EDA tools via C2S
Market Scale Target $100–110B by 2030 India currently consumes $50B in semiconductors but produces only $2–3B domestically. ISM 2.0 targets producing chips for 70–75% of domestic applications by 2029.
The Macro Gap That Makes Vervesemi’s Bet Compelling

India consumes ~$50 billion in semiconductors annually. Domestic manufacturing contributes only $2–3 billion — a 94–96% import dependency gap. By 2030, consumption is projected to hit $100–110 billion. Every analog chip that Vervesemi supplies to an Indian space organisation, EV motor controller, or industrial sensor company displaces an import. The government has every incentive to ensure Vervesemi scales: its IP stays in India, its engineers stay in India, and its royalty flows stay in India.

Deep-Tech Funding Week in India — February 2026

Vervesemi’s raise is part of a broader signal: deep tech investor appetite is accelerating across multiple verticals simultaneously:

Company Amount Sector Signal
Vervesemi  $10M Series A Semiconductors Oversubscribed; Ashish Kacholia + Unicorn India Ventures; space-grade silicon now production-ready
ValueQuest PE Fund ₹1,500 crore Deep Tech PE Pure domestic LP base; signals Indian HNI + institution confidence in long-cycle deep tech returns
Peptris ₹70 crore Series A Drug Discovery AI-driven molecule design; pharma deep tech getting institutional capital; adjacent to semiconductor AI
ISM 2.0 (Government) ₹40,000 crore ECMS + ₹1,000 crore ISM2 Policy / Semiconductor Macro tailwind: Budget 2026 creates largest-ever semiconductor policy outlay; private capital follows public signal

STARTUPFEED INSIGHT

The Design-IP Play: Most of the global semiconductor value chain narrative focuses on fabs — TSMC, Samsung, Intel’s foundry ambitions. But the highest-margin, most durable business in semiconductors is IP licensing. Arm Holdings earns royalties on 95%+ of the world’s smartphones without owning a single fab. Vervesemi, at $10M Series A, is a decade away from that scale — but the architecture is the same: own the IP blocks, license them to foundry partners, collect royalties per chip manufactured. India has never produced a global analog IP licensor. Vervesemi is explicitly building toward that position.
For Founders: Vervesemi proves that 7-year patient capital in deep hardware tech gets rewarded — but only if you have verifiable customer wins before raising Series A. ‘Space organisation production contract’ is the kind of anchor customer that transforms your credibility with every subsequent investor conversation.
For Investors: The Ashish Kacholia + Unicorn India Ventures co-lead is a template: combine a marquee public-market name (for HNI signaling) with a specialist deep tech fund (for due diligence credibility). Expect this structure to be replicated across 5–8 semiconductor deals in India over the next 18 months.
For Policy Makers: Vervesemi’s DLI recognition + C2S award + private Series A closing — oversubscribed — is exactly the public-private flywheel ISM 2.0 is designed to create. The next step: government should create a ‘Semiconductor IP Fund’ that co-invests in fabless IP startups at seed stage, the way Israel’s Yozma programme built that nation’s chip design ecosystem in the 1990s.
Our Prediction: Vervesemi will announce its first global OEM licensing deal (likely a European or Japanese industrial automation player) within 12 months of this raise — the GTM capital is now available to make those deals happen. By 2028, expect a Series B of $30–40 million, led by a global semiconductor or industrials-focused fund (think Motorola Solutions Ventures, Siemens Energy Ventures, or a Korean/Taiwanese strategic investor). The space-grade silicon business will become Vervesemi’s headline case study that unlocks the premium valuation. Within 3 years, it will be India’s most cited analog semiconductor IP company — the country’s answer to Arm for the industrial edge.

 

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